// Cell name: ece3663F1
// This circuit implements the function F1 = (AB + BC + AC)'
// It has sizing parameters and parameterized AD, AS, PD, PS.
// Edited by Team XOR; we improved the circuit from 2008 by removing
// two transistors. The old implementation had 12 transistors while
// this implementation only uses 10 transistors. We were able to 
// remove one transistor for both the PUN and PDN by simplifying the F1 equation to F1=(A(B+C)+BC)'
// We also sized the implementation to have equal pull-up and pull-down networks.


subckt ece3663F1 Vdd Vss A B C Out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
   P0 (Out B Node2 Vdd) ami06P w=3*wp l=lp as=1.5u*3*wp ad=1.5u*3*wp \
	ps=3u+3*wp pd=3u+3*wp m=mult
   P2 (Node2 C Node1 Vdd) ami06P w=3*wp l=lp as=1.5u*3*wp ad=1.5u*3*wp \
   	ps=3u+3*wp pd=3u+3*wp m=mult
   P3 (Node1 B Vdd Vdd) ami06P w=3*wp l=lp as=1.5u*3*wp ad=1.5u*3*wp \
   	ps=3u+3*wp pd=3u+3*wp m=mult
   P1 (Out C Node2 Vdd) ami06P w=3*wp l=lp as=1.5u*3*wp ad=1.5u*3*wp \
   	ps=3u+3*wp pd=3u+3*wp m=mult
   P4 (Node2 A Vdd Vdd) ami06P w=1.5*wp l=lp as=1.5u*1.5*wp ad=1.5u*1.5*wp \
   	ps=3u+1.5*wp pd=3u+1.5*wp m=mult
   N4 (Out C Node4 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
   	ps=3u+2*wn pd=3u+2*wn m=mult
   N3 (Node4 B Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
   	ps=3u+2*wn pd=3u+2*wn m=mult
   N2 (Out C Node3 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
   	ps=3u+2*wn pd=3u+2*wn m=mult
   N1 (Out B Node3 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
   	ps=3u+2*wn pd=3u+2*wn m=mult
   N0 (Node3 A Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
   	ps=3u+2*wn pd=3u+2*wn m=mult
ends ece3663F1
//Ends subcircuit definition